The unsurpassed crossbar switch design of the Silicon Graphics® Octane2
system provides excellent levels of interactivity with critical data transfers,
such as loading a 3D model from memory to the screen. The 1.0GB per second
peak main memory bandwidth and 1.6GB per second peak bandwidth between
subsystems ensure that you experience smooth, fluid operations while
completing even the most complex tasks. The Octane2 workstation's 8GB memory
capacity gives you increased power to handle bigger data sets for more
accurate analysis in less time. Configured with single or dual MIPS®
processors, Octane2 delivers the power to quickly complete one task or
simultaneously tackle multiple tasks such as design and analysis or motion
modeling and behavior scripting. You can perform more tasks on more data
than ever before at the desktop level. The exceptional system responsiveness
means that you can focus completely on the problem you are solving, while
working intuitively to get the job done better and faster.
| Key Architecture Features |
- 1.0GB/sec main memory peak bandwidth
- 1.6GB/sec peak
- 64K primary cache, 2MB secondary cache
- 32 or 64-bit binaries
- Symmetric multiprocessing
- Priority I/O
- Optimized front side bus
Octane2 I/O
- Two full- and one half-size optional industry-standard PCI slots for 32- and 64-bit wide PCI devices
- Three 3.5-inch Ultra SCSI drive bays
- Four XIO slots for graphics, networking, and storage cards
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| XIO Option Cards |
All have the same form factor and cover one or two slots.
- Storage XIO Option Cards
- Fibre Channeltwo ports (one slot)
- UltraSCSIfour ports (one slot)
- Networking XIO Option Cards:
- Fast Ethernetfour ports (one slot)
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| Processors |
The Silicon Graphics Octane2 visual workstation is powered by the 64-bit MIPS®
R14000A processor.
- R14000A--The New Computational Leader
With out-of-order execution, large flexible caches, and superscalar design,
R14000A brings top performance to real-world codes.
- R14000A CPU:
- 600 MHz
- Four-way superscalar, 64-bit architecture
- Out-of-order instruction execution
- Five separate execution units
- MIPS 4 instruction set
- 32KB two-way set-associative on-chip instruction cache
- 2MB fast secondary cache
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